Refined Bounds on Signature Analysis Aliasing for Random Testing

Simple Bounds on Serial Signature Analysis Aliasing for Random Testing

It is shown that the aliasing probability is bounded above by (1 + E ) / L M 1/L ( E small for large L) for test lengths L less than the period, L,, of the signature polynomial; for test lengths L that are multiples of L,, the aliasing probability is bounded above by 1; and, for test lengths L greater than L, and not a multiple of L,, the aliasing probability is bounded above by 2 / ( L c + 1)....

Parallel Signatur Analysis Design with Bounds on Aliasing

This paper presents parallel signature design techniques that guarantee the aliasing probability to be less than 2/L, where L is the test length. Using y signature samples, a parallel signature analysis design is proposed that guarantees the aliasing probability to be less than (y/L). Inaccuracies and incompleteness in previously published bounds on the aliasing probability are discussed. Simpl...

Signature Testing of Analog-to-digital Converters

− When testing an analog-to-digital converter (ADC) by automatic test equipment (ATE), the latter is capable of performing extensive processing of output responses of the ADC. This allows detection of virtually any fault. However, the cost of ATE is quite high. As well, the external bandwidth of ATE is normally lower than the internal bandwidth of the ADC being tested, which makes it difficult ...

Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing"

Zero Aliasing for Modeled Faults

When using Built-In Self Test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is compacted into a signature which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division. The compacting function is a many-to-one function and as a res...